1. Field of the Invention
The present invention relates to a complementary MOS semiconductor device having a resistance circuit formed on an SOI (silicon on insulator) substrate.
2. Description of the Related Art
Complementary MOS (CMOS) semiconductor integrated circuits having resistance circuits have been heretofore used in large numbers.
The resistance circuits include resistors used in a bleeder voltage-dividing circuit for voltage-dividing a voltage or in a CR circuit for setting a time constant. In analog semiconductor devices (such as comparators and operational amplifiers), voltage detectors, and power management semiconductor devices (such as constant voltage regulators and switching regulators), especially in analog circuits, voltages need to be divided accurately by a bleeder voltage-dividing circuit. Therefore, the characteristic that the bleeder resistor is required to have is a high resistance ratio accuracy. For example, in a voltage detector (VD), the ratio of the area of the resistance circuit to the chip area is very large and so reducing the area of the resistive element at high accuracy will lead to a decrease in the chip area. Consequently, the cost can be curtailed.
Polycrystalline silicon is generally used as the material of this resistive element. Where polycrystalline silicon is used as a resistor, the resistance value depends greatly on the crystal grain diameter of the polycrystalline silicon, on the grain boundaries, and on the film thickness. Therefore, the resistance value varies according to the state of fabrication equipment for depositing polycrystalline silicon by a CVD (chemical vapor deposition) method. Furthermore, polycrystalline silicon is patterned and etched to form resistors. If the area of a resistor is reduced, conspicuous variations in resistance value appear due to variations in etching. This makes it difficult to maintain the resistance ratio accuracy of the resistance circuit.
Where this resistor is formed by making use of the silicon active layer of an SOl substrate that is a single crystal of silicon, variations in resistance dependent on grain boundaries do not exist at all because there are no grain boundaries in the resistor. Furthermore, it is possible to increase the resistance of the resistor and to reduce the area. Consequently, it is quite effectively used as a resistor. In addition, where silicon etching is used instead of LOCOS isolation to pattern a single-crystal silicon resistor, the single-crystal silicon is processed at higher accuracy than polycrystalline silicon. Therefore, etching variations can be reduced. In consequence, single-crystal silicon is advantageously used as a resistor (for example, see Reference 1 (JP-A-2001-144254 (FIG. 1″)).
An accurate voltage division ratio, i.e., a high resistance ratio accuracy, is required as a characteristic for a resistor used in an analog circuit. Therefore, it is necessary to minimize resistance value variations due to variations in the potential applied to the resistor. Accordingly, in a bulk CMOS process, wells for fixing the potential are formed under the resistor.
However, where the silicon active layer in the SOI substrate is used as a resistor, fine wells are formed densely in the semiconductor support substrate portion under the resistor because of the presence of a buried insulating layer. Furthermore, it is difficult to provide voltage-dividing control of the wells. This incurs the problem that the resistance value is varied by potential variations.